1. Field of the Invention
The present invention relates to a semiconductor chip assembly, and more particularly to a semiconductor chip assembly with a contact terminal having a plated metal peripheral sidewall portion and methods of making such an assembly.
2. Description of the Related Art
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. The connection media is typically an array of metallic leads (e.g., a lead fame) or a support circuit (e.g., a substrate), although the connection can be made directly to a circuit panel (e.g., a mother board). Several connection techniques are widely used. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding.
A semiconductor chip assembly is subsequently connected to another circuit such as a printed circuit board (PCB) or mother board during the next level assembly. Different semiconductor assemblies are connected to the next level assembly in different ways. For instance, ball grid array (BGA) packages contain an array of solder balls, and land grid array (LGA) packages contain an array of metal pads that receive corresponding solder traces on the PCB.
Semiconductor chip assemblies such as BOA packages that include solder-containing contact terminals normally require a solder reflow operation at an elevated temperature, for instance to harden previously deposited solder paste portions. Low temperature solder with a melting point below 200xc2x0 C. is typically a tin-lead alloy and lead-based materials are becoming far less popular due to environmental concerns over disposing of toxic materials and leaching of toxic materials into ground water supplies. High temperature solder with a melting point between 200-300xc2x0 C. can result in damage to the semiconductor chip assembly during the reflow operation. The damage includes die attach delamination, encapsulant delamination and epoxy substrate warping, and these problems are compounded when the solder is subsequently reflowed during the next level assembly.
Thermo-mechanical wear or creep of the solder joints that connect the semiconductor chip assembly to the next level assembly is a major cause of failure in most board assemblies. This is because non-uniform thermal expansion and/or contraction of different materials causes mechanical stress on the solder joints.
Thermal mismatch induced solder joint stress can be reduced by using materials having a similar coefficient of thermal expansion (CTE). However, due to large transient temperature differences between the chip and other materials during power-up of the system, the induced solder joint stress makes the assembly unreliable even when the chip and the other materials have closely matched thermal expansion coefficients.
Thermal mismatch induced solder joint stress can also be reduced by proper design of the support circuit For instance, BGA and LGA packages have been designed with pillar post type contact terminals that extend above the package and act as a stand-off or spacer between the package and the PCB in order to absorb thermal stress and reduce solder joint fatigue. The higher the aspect ratio of the pillar, the more easily the pillar can flex to follow expansion of the two ends and reduce shear stress.
Conventional approaches to forming the pillar either on a wafer or a separate support circuit include a bonded interconnect process (BIP) and plating using photoresist.
BIP forms a gold ball on a pad of the chip and a gold pin extending upwardly from the gold ball using a thermocompression wire bonder. Thereafter, the gold pin is brought in contact with a molten solder bump on a support circuit, and the solder is reflowed and cooled to form a solder joint around the gold pin. A drawback to this approach is that when the wire bonder forms the gold ball on the pad it applies substantial pressure to the pad which might destroy active circuitry beneath the pad. In addition, gold from the pin can dissolve into the solder to form a gold-tin intermetallic compound which mechanically weakens the pin and therefore reduces reliability.
U.S. Pat. No. 5,722,162 discloses fabricating a pillar by electroplating the pillar on a selected portion of an underlying metal exposed by an opening in photoresist and then stripping the photoresist. Although it is convenient to use photoresist to define the location of the pillar, electroplating the pillar in an opening in the photoresist has certain drawbacks. First, the photoresist is selectively exposed to light that initiates a reaction in regions of the photoresist that correspond to the desired pattern. Since photoresist is not fully transparent and tends to absorb the light, the thicker the photoresist, the poorer the penetration efficiency of the light. As a result, the lower portion of the photoresist might not receive adequate light to initiate or complete the intended photo-reaction. Consequently, the bottom portion of the opening in the photoresist might be too narrow, causing a pillar formed in the narrowed opening to have a diameter that decreases with decreasing height. Such a pillar has a high risk of fracturing at its lower portion in response to thermally induced stress. Furthermore, photoresist residue on the underlying metal might cause the pillar to have poor quality or even prevent the pillar from being formed. Second, if the photoresist is relatively thick (such as 100 microns or more), the photoresist may need to be applied with multiple coatings and receive multiple light exposures and bakes, which increases cost and reduces yield. Third, if the photoresist is relatively thick, the electroplated pillar may be non-uniform due to poor current density distribution in the relatively deep opening. As a result, the pillar may have a jagged or pointed top surface instead of a flat top surface that is better suited for providing a contact terminal for the next level assembly.
In view of the various development stages and limitations in currently available semiconductor chip assemblies, there is a need for a semiconductor chip assembly that is cost-effective, reliable, manufacturable, and provides excellent mechanical and electrical performance.
An object of the present invention is to provide a semiconductor chip assembly that provides a low cost, high performance, high reliability package.
Another object of the present invention is to provide a convenient, cost-effective method for manufacturing semiconductor chip assemblies as grid arrays or other structures.
In accordance with an aspect of the invention, a method of making a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, providing a conductive trace and a metal base, wherein the conductive trace includes a routing line and a contact terminal, the routing line is disposed outside the metal base, the contact terminal extends from the routing line through the metal base, the contact terminal includes a plated metal that contacts and extends through the metal base, the plated metal forms a peripheral sidewall portion of the contact terminal, and the plated metal surrounds a central surface area without extending into the central surface area, then mechanically attaching the chip to the conductive trace, removing a portion of the metal base that contacts the plated metal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.
The method may include mechanically attaching the chip to the conductive trace using an insulative adhesive, and then forming a through-hole through the adhesive that exposes the routing line and the pad after removing the portion of the metal base and before forming the connection joint.
The method may also include providing the conductive trace, an insulative base and the metal base, and then mechanically attaching the chip to the insulative base using the adhesive such that the metal base is disposed on a side of the insulative base that faces away from the chip and the routing line is disposed on a side of the insulative base that faces towards the chip.
The method may also include forming a via that extends through the metal base, the insulative base and the metal layer and has opposing open ends, and then depositing the contact terminal into the via.
The method may also include forming a first plating mask on the metal base and a second plating mask on the metal layer, and then forming the via through the metal base, the insulative base, the metal layer and the plating masks.
The method may also include depositing the contact terminal into the via by plating the plated metal into the via and on the metal base without plating the plated metal on the metal layer and then plating the plated metal into the via and on the metal layer.
The method may also include depositing the contact terminal into the via by plating the plated metal as a first plated metal portion on the metal base and a second plated metal portion on the metal layer without the first and second plated metal portions contacting one another, and then plating the plated metal into the via such that the first and second plated metal portions contact one another.
The method may also include depositing the contact terminal into the via by electroplating the plated metal as a firs plated metal portion on the metal base and a second plated metal portion on the metal layer without the first and second plated metal portions contacting one another, rendering the insulative base in the via catalytic to electroless plating, and then electrolessly plating the plated metal into the via as a third plated metal portion that contacts the first and second plated metal portions and the insulative base.
The method may also include depositing the contact terminal into the via by plating the plated metal into the via and on the metal base without plating the plated metal on the metal layer, and then depositing a conductive adhesive into the via and on the plated metal and the metal layer.
The method may also include depositing the contact terminal into the via by plating the plated metal as a first plated metal portion on the metal base and a second plated metal portion on the metal layer without the first and second plated metal portions contacting one another, and then depositing a conductive adhesive into the via and on the first and second plated metal portions.
The method may also include forming a photoresist layer over the metal layer, etching the metal layer using the photoresist layer as an etch mask such that an unetched portion of the metal layer forms at least a portion of the routing line, and then removing the photoresist layer.
The method may also include filling an insulator into the contact terminal that extends from the routing line through the insulative base and the metal base and contacts the plated metal after mechanically attaching the chip and before removing the portion of the metal base. Preferably, the insulator is a transfer molded encapsulant that contacts and covers a distal end of the contact terminal that faces away from the chip, and contacts the peripheral sidewall portion of the contact terminal. It is also preferred that the encapsulant contacts the chip, the insulative base and the routing line outside the via. It is also preferred that the encapsulant is compressible and permits the contact terminal to exhibit elastic deformation in response to externally applied pressure.
In accordance with another aspect of the invention, a semiconductor chip assembly includes a semiconductor chip, an insulative base, a conductive trace and a connection joint. The chip includes a conductive pad. The conductive trace that includes a routing line and a contact terminal. The routing line is disposed on a side of the insulative base that faces towards the chip, and the contact terminal extends from the routing line through the insulative base and protrudes from a side of the insulative base that faces away from the chip. The contact terminal includes a plated metal that forms a peripheral sidewall portion, and the plated metal surrounds a central surface area without extending into the central surface area. The connection joint contacts and electrically connects the routing line and the pad.
The assembly may include a conductive adhesive that extends from the routing line through the insulative base and contacts and electrically connects the plated metal and the routing line.
The assembly may also include an encapsulant that extends through the routing line, the insulative base and the contact terminal and contacts the distal end and peripheral sidewall portion of the contact terminal.
An advantage of the present invention is that the semiconductor chip assembly includes a conductive trace with an additively formed contact terminal that includes a plated metal that provides a peripheral sidewall portion of the contact terminal. The plated metal can surround a central surface area without extending into the central surface area. A compressible material such as a transfer molded encapsulant can be filled into the central surface area and extend from the routing line across the insulative base to the distal end of the contact terminal, thereby permitting the contact terminal to exhibit compliance for the next level assembly. Alternatively, a conductive adhesive can be filled into the central surface area and extend from the routing line across the insulative base to the plated metal, thereby permitting more rapid manufacture of the contact terminal since the plated metal need not extend through the insulative base. Another advantage is that the contact terminal can be solder-free. Another advantage is that the assembly can be manufactured using low temperature processes which reduces stress and improves reliability. A further advantage is that the assembly can be manufactured using well-controlled wet chemical processes which can be easily implemented by circuit board, lead frame and tape manufacturers. Still another advantage is that the assembly can be manufactured using materials that are compatible with copper chip and lead-free environmental requirements.
These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.